CMG-3T Digitizer

Three-component digitizer for a Güralp CMG-3T 120 s broadband (T35286): three ADS1220s for velocity, an ADS1115 for mass positions, on a Raspberry Pi. Two ElectroCookie solderable breadboards in a 3D-printed box. Drawings, tables and test steps; the software is in pi/ and pc/.

Sensitivity499 V/(m/s)at the ADC · 0.489 nm/s per count

Full scale±4.1 mm/ssensor clips at 13 mm/s

Build2 boards23 + 14 parts · 13 + 13 jumpers

Overview

The sensor already delivers flat velocity from 120 s to 50 Hz on low-impedance differential outputs, so there is no preamp: each component gets a matched divider onto a 1.668 V pedestal and its own ADS1220. All three converters share the Pi’s SPI bus.

Sensor	1500 V/(m/s)	2 × 750, differential · 120 s – 50 Hz flat
Divider gain	0.3329	4.99 k / (4.99 k + 10 k), both legs · common mode 1.668 V
At the ADC	499 V/(m/s)	Gain 1, PGA bypassed, internal 2.048 V reference
One count	0.489 nm/s	244.1 nV / 499 V/(m/s)
Full scale	±4.1 mm/s	Deliberately below the sensor’s clip; the noise floor matters more
Floor, expected	~1.5 nm/s/√Hz	Measured with the inputs shorted inside the ADS1220, turbo mode, 0.5–5 Hz
Rate	150 SPS	Single-shot turbo conversions (5.5 ms), all three started together on a UTC grid, resampled to 100 SPS logged. Turbo is ~5× quieter than normal mode at the same rate
Mass positions	±8.6 V	ADS1115 via 90.9 k / 10 k to VREF: V_mass = (V_in − 0.9009 V_REF) / 0.0991, with V_REF read on A3 every time (the LM4040 is 1%: assuming 2.50 V would put the mass readings up to 0.36 V off)

Parts

Every part, grouped by where it goes. Qty is what the board uses; “of N” is what was bought. A blank DigiKey cell means DigiKey doesn’t sell it.

Part	Maker	DigiKey	Qty	Refs	Notes
ADC board
ADS1220 module	generic		3 (+1)	ADCZ, ADCN, ADCE	Purple 16-pin module. Not stocked by DigiKey. Meter each: AVDD–DVDD ~0 Ω, CLK–DGND ~10 kΩ
YR1B4K99CC	TE	1712-YR1B4K99CCCT-ND	6 (of 8)	RaZ, RapZ, RaN, RapN, RaE, RapE	4.99 kΩ 0.1%. Across the GND rail to VREF
MFP-25BRD52-10K	Yageo	10KADCT-ND	6 (of 8)	RbZ, RbpZ, RbN, RbpN, RbE, RbpE	10 kΩ 0.1%. Looks like the 4.99k: meter before soldering
B32529C0104J000	TDK	495-1103-ND	3	CdifZ, CdifN, CdifE	100 nF film. Flat under each module, fitted before the sockets
LM4040DIZ-2.5/NOPB	TI	LM4040DIZ-2.5/NOPB-ND	1	VR1	2.5 V shunt reference, TO-92, H27–H29
MFR-25FRF52-2K87	Yageo	13-MFR-25FRF52-2K87CT-ND	2	Rfd1, Rfd2	2.87 kΩ 1%, in parallel, Pi 5 V to VREF
C320C104K5R5TA	KEMET	399-4264-ND	2	Cref, Cd	100 nF X7R ceramic. VREF rail and 3V3 rail decoupling
PPTC081LFBN-RC	Sullins	S7006-ND	3	Module sockets	8-pin female header. Each module takes one whole 8-pin strip plus a 6-pin and a 1-pin piece; cut through a contact
ElectroCookie solderable breadboard	ElectroCookie		1	—	Not DigiKey
AUX board
ADS1115 breakout, 10-pin	generic		1	U1	Mass positions. Blue board, single row VDD…A3; stands upright in D3–D12. Not DigiKey. Check the chip reads BOGI (BRPI = ADS1015). Some cheap boards carry fake chips: at PGA ±2.048 V a 2.47 V input must read 32767
MFR-25FBF52-90K9	Yageo	90.9KXBK-ND	3 (of 5)	RmZ, RmN, RmE	90.9 kΩ 1%. Mass-position divider, top leg
MFR-25FBF52-10K	Yageo	10.0KXBK-ND	3 (of 5)	RrZ, RrN, RrE	10 kΩ 1%. Divider bottom leg to VREF. Keep apart from the 0.1% 10k
MFR-25FBF52-1K	Yageo	1.00KXBK-ND	3 (of 5)	Rk1–Rk3	1 kΩ 1%. Optocoupler LED resistors
LTV-817	Lite-On	160-1366-5-ND	3 (of 4)	OK1–OK3	Optocoupler, DIP-4. Pin-1 dot top right, in row F
1N5819	onsemi or any	1N5819FSCT-ND	1 (of 2)	D1	Schottky, 12 V reverse-polarity guard. C13→C17, band toward 17
ElectroCookie solderable breadboard	ElectroCookie		1	—	Not DigiKey
Box, cables and Pi
Panel-mount DC jack, 5.5 / 2.1 mm			2	—	VIN: 12 V adapter in, to AUX A13 (+) / A14 (−). VOUT: the sensor power lead, from AUX A17 (+) / A16 (−)
DC plug, 5.5 / 2.1 mm			1	—	On the box end of the sensor power lead, for VOUT
Momentary pushbutton, NO, panel mount, 7 mm			3	—	LOCK / UNLOCK / CENTRE in the box’s front wall, in parallel with OK1–OK3
Cat6 keystone jack, punch-down			2	—	Box front wall, two colours; wired T568B
Ethernet patch cable, stranded, 3 m			2	—	SIG and CTL, two colours. Not solid-core
Two-core lead, ~20 AWG, 3 m			1	—	Sensor power: red to pin c, black to pin b
Dupont female-to-bare leads			~30	—	Pi harness (19 Pi pins) and the sensor-pin ends
Standoffs ~25 mm, with screws			4	—	ADC above AUX
M2 hex standoffs, male–female, 4 mm stud, with nuts			8	—	Four under the board stack, studs through the box floor; four for the Pi on the box’s side wall. Nuts 6 mm across flats
3D-printed box: base, lid			1	—	`enclosure/`: STLs and the script that makes them. Print `fit_test.stl` first
Raspberry Pi 5, 4 GB	Raspberry Pi		1	—	Dedicated to this station; mounts outside the box on its right wall
Pi 5 27 W USB-C supply, active cooler, 32 GB microSD, right-angle USB-C adapter	Raspberry Pi		1	—	The USB-C port faces down, 12 mm above the table
Optional: a real plug, if the Dupont sockets ever give intermittents
PT06E-16-26S(SR)	Amphenol	PT06E-16-26S(SR)-ND	1	—	Mating plug, solder cup. A MS3116F16-26S clone also works; no W/X/Y/Z suffix
0319-1-15-15-18-27-04-0	Mill-Max	ED1284-ND	17	—	For a 3D-printed plug: socket contact for the 1.016 mm sensor pins, solder tail

ADC board

The upper of the two stacked boards. Rails top to bottom: 3V3, GND, GND, VREF. Z, N and E modules at columns 1–8, 10–17 and 19–26, each with its divider in the lower bank; the LM4040 at columns 27–29. Sensor leads land from the bottom edge, Pi wires from the top.

Thirteen jumpers plus PJ at column 30, and bus wires B1–B6 (coloured arcs) in rows G and H, top side, beneath the modules. The dashed red circle on each module is the AVDD pin that gets no socket. Blue stubs are wires that solder straight into the board, labelled with where they come from.

Ref	Value	DigiKey	Holes	Nets, in pin order	Notes
ADCZ	ADS1220 Z	— (generic module)	D1D3…D8I1…I8	AGNDREFP0…AIN0DGND…DRDY	Label up, AIN0 and DRDY at the right. Digital side in an 8-pin female strip in row I. Analog side in a 1-pin strip at AGND and a 6-pin strip at REFP0…AIN0; the AVDD position gets no socket, and its pin must not touch the board: clip it off if in doubt (AVDD is tied to DVDD on the module)
RbpZ	10k	10KADCT-ND	B2B7	SIGN_ZAIN1_Z	Minus leg, 10 kΩ 0.1%. Lies flat over the four unused module strips
RbZ	10k	10KADCT-ND	B8B9	AIN0_ZSIGP_Z	Plus leg, 10 kΩ 0.1%. Stands on end
RapZ	4.99k	1712-YR1B4K99CCCT-ND	A7VREF rail, col 7	AIN1_ZVREF	4.99 kΩ 0.1% to the reference. Lies across the GND rail
RaZ	4.99k	1712-YR1B4K99CCCT-ND	A8VREF rail, col 8	AIN0_ZVREF	4.99 kΩ 0.1% to the reference. Lies across the GND rail
CdifZ	100n	495-1103-ND	E7E8	AIN1_ZAIN0_Z	100 nF film. Fit before the module: lies flat under it, body toward the channel
ADCN	ADS1220 N	— (generic module)	D10D12…D17I10…I17	AGNDREFP0…AIN0DGND…DRDY	Label up, AIN0 and DRDY at the right. Digital side in an 8-pin female strip in row I. Analog side in a 1-pin strip at AGND and a 6-pin strip at REFP0…AIN0; the AVDD position gets no socket, and its pin must not touch the board: clip it off if in doubt (AVDD is tied to DVDD on the module)
RbpN	10k	10KADCT-ND	B11B16	SIGN_NAIN1_N	Minus leg, 10 kΩ 0.1%. Lies flat over the four unused module strips
RbN	10k	10KADCT-ND	B17B18	AIN0_NSIGP_N	Plus leg, 10 kΩ 0.1%. Stands on end
RapN	4.99k	1712-YR1B4K99CCCT-ND	A16VREF rail, col 16	AIN1_NVREF	4.99 kΩ 0.1% to the reference. Lies across the GND rail
RaN	4.99k	1712-YR1B4K99CCCT-ND	A17VREF rail, col 17	AIN0_NVREF	4.99 kΩ 0.1% to the reference. Lies across the GND rail
CdifN	100n	495-1103-ND	E16E17	AIN1_NAIN0_N	100 nF film. Fit before the module: lies flat under it, body toward the channel
ADCE	ADS1220 E	— (generic module)	D19D21…D26I19…I26	AGNDREFP0…AIN0DGND…DRDY	Label up, AIN0 and DRDY at the right. Digital side in an 8-pin female strip in row I. Analog side in a 1-pin strip at AGND and a 6-pin strip at REFP0…AIN0; the AVDD position gets no socket, and its pin must not touch the board: clip it off if in doubt (AVDD is tied to DVDD on the module)
RbpE	10k	10KADCT-ND	B20B25	SIGN_EAIN1_E	Minus leg, 10 kΩ 0.1%. Lies flat over the four unused module strips
RbE	10k	10KADCT-ND	B26B27	AIN0_ESIGP_E	Plus leg, 10 kΩ 0.1%. Stands on end
RapE	4.99k	1712-YR1B4K99CCCT-ND	A25VREF rail, col 25	AIN1_EVREF	4.99 kΩ 0.1% to the reference. Lies across the GND rail
RaE	4.99k	1712-YR1B4K99CCCT-ND	A26VREF rail, col 26	AIN0_EVREF	4.99 kΩ 0.1% to the reference. Lies across the GND rail
CdifE	100n	495-1103-ND	E25E26	AIN1_EAIN0_E	100 nF film. Fit before the module: lies flat under it, body toward the channel
VR1	LM4040 2.5V	LM4040DIZ-2.5/NOPB-ND	H27H28H29	GNDVREFGND	TO-92, either way round: the middle pin is the cathode and both outer pins go to GND (jumpers 10, 11)
Rfd1	2.87k	13-MFR-25FRF52-2K87CT-ND	B28B29	VREFP5	Feeds the reference from the Pi 5 V. Stands on end
Rfd2	2.87k	13-MFR-25FRF52-2K87CT-ND	C28C29	VREFP5	In parallel with Rfd1: 1.44 kΩ gives 1.7 mA; the dividers take up to 1.3 mA
Cref	100n	399-4264-ND	GND btm, col 23VREF rail, col 23	GNDVREF	Decouples the VREF rail. Any 100 nF ceramic
Cd	100n	399-4264-ND	3V3 rail, col 1GND top, col 1	3V3GND	3V3 rail decoupling at the far end from the Pi wire

Jumpers

#	Jumper	Net
1	A1→GND btm, col 1	GND
2	J2→3V3 rail, col 2	3V3
3	J3→GND top, col 3	GND
4	A10→GND btm, col 10	GND
5	J11→3V3 rail, col 11	3V3
6	J12→GND top, col 12	GND
7	A19→GND btm, col 19	GND
8	J20→3V3 rail, col 20	3V3
9	J21→GND top, col 21	GND
10	J27→GND top, col 27	GND
11	J29→GND top, col 29	GND
12	F28→E28	VREF
13	A28→VREF rail, col 28	VREF
B1	H5→H14	SCLK · bus wire, top side, beneath the modules
B2	G14→G23	SCLK · bus wire, top side, beneath the modules
B3	H6→H15	MOSI · bus wire, top side, beneath the modules
B4	G15→G24	MOSI · bus wire, top side, beneath the modules
B5	H7→H16	MISO · bus wire, top side, beneath the modules
B6	G16→G25	MISO · bus wire, top side, beneath the modules
PJ	GND top, col 30→GND btm, col 30	GND · ties the two ground rails; run it beside column 30 or on the underside

Wires in

Hole	Net	From
A2	SIGN_Z	sensor B · Z −
A9	SIGP_Z	sensor A · Z +
J4	CS_Z	CS · pin 18 · GPIO24
J5	SCLK	SCLK · pin 23 · GPIO11
J6	MOSI	MOSI · pin 19 · GPIO10
J7	MISO	MISO · pin 21 · GPIO9
J8	DRDY_Z	DRDY · pin 13 · GPIO27
A11	SIGN_N	sensor D · N −
A18	SIGP_N	sensor C · N +
J13	CS_N	CS · pin 22 · GPIO25
J17	DRDY_N	DRDY · pin 15 · GPIO22
A20	SIGN_E	sensor F · E −
A27	SIGP_E	sensor E · E +
J22	CS_E	CS · pin 29 · GPIO5
J26	DRDY_E	DRDY · pin 31 · GPIO6
A29	P5	Pi 5V · pin 2
3V3 rail, col 30	3V3	Pi 3V3 · pin 1
GND top, col 28	GND	Pi GND · pin 6
GND btm, col 24	GND	sensor N · sig gnd
D28	VREF	to AUX · VREF

AUX board

Sits under the ADC board. Mass positions, the Pi’s lock / unlock / centre outputs, and the 12 V pass-through. Top rails: VREF (wired from the ADC board) and GND; the rail next to row A is unused and the bottom rail is GND for the ADS1115 (PJ ties it to the top GND rail). The 12 V strips at columns 13–17 and the optocoupler outputs at 19–26 touch no rail, so the sensor side stays separate from the Pi’s ground.

Thirteen jumpers plus PJ, which ties the two ground rails (the bottom one serves the ADS1115; the rail next to row A is deliberately unused, so nothing live sits beside the 12 V and sensor-line holes). The ADS1115 stands upright in D3–D12; jumpers 10–13 carry A0–A3 across the channel to the divider strips.

Ref	Value	DigiKey	Holes	Nets, in pin order	Notes
U1	ADS1115	— (generic module)	D3…D12	VDD GND SCL SDA ADDR ALRT A0 A1 A2 A3	Generic blue ADS1115 board, 10-pin single row. Stands upright on its header in D3–D12, chip side toward row A. VDD…ALRT sit on strips 3–8 (the Pi wires and jumpers 1–2 serve them); A0…A3 on strips 9–12, carried across the channel by jumpers 10–13 to the Z, N, E and VREF strips. ADDR to GND (jumper 2) = I²C address 0x48. A3 is on VREF (jumpers 3, 13) so the software measures the reference. ALRT stays open. Chip marking BOGI (BRPI is an ADS1015, 12-bit: reject)
RmZ	90.9k	90.9KXBK-ND	I7I12	MZMASS_Z	Mass-position input leg
RrZ	10k	10.0KXBK-ND	J7VREF rail, col 7	MZVREF	To VREF: shifts ±8.6 V into 1.40–3.11 V
RmN	90.9k	90.9KXBK-ND	H6H11	MNMASS_N	Mass-position input leg
RrN	10k	10.0KXBK-ND	J6VREF rail, col 6	MNVREF	To VREF
RmE	90.9k	90.9KXBK-ND	I5I1	MEMASS_E	Mass-position input leg
RrE	10k	10.0KXBK-ND	J5VREF rail, col 5	MEVREF	To VREF
D1	1N5819	1N5819FSCT-ND	C13C17	V12INV12	Reverse-polarity guard in the sensor’s +12 V. Band toward column 17. Drops ~0.4 V
OK1	LTV-817	160-1366-5-ND	F20F19E19E20	LED_UGNDYCTL_U	CENTRE. Pin-1 dot top right (F20): pin 1 anode F20, 2 cathode F19, 3 emitter E19, 4 collector E20. LED from the Pi; the transistor pulls U to Y
Rk1	1k	1.00KXBK-ND	H20H21	LED_UGPIO_U	Stands on end. LED current from the Pi GPIO: (3.3 − 1.2 V) / 1 k = 2 mA
OK2	LTV-817	160-1366-5-ND	F23F22E22E23	LED_WGNDYCTL_W	UNLOCK, same orientation, dot at F23. Pulls W to Y
Rk2	1k	1.00KXBK-ND	H23H24	LED_WGPIO_W	Same
OK3	LTV-817	160-1366-5-ND	F26F25E25E26	LED_XGNDYCTL_X	LOCK, same orientation, dot at F26. Pulls X to Y
Rk3	1k	1.00KXBK-ND	H26H27	LED_XGPIO_X	Same

Jumpers

#	Jumper	Net
1	A4→btm rail, col 4	GND
2	A7→btm rail, col 7	GND
3	J4→VREF rail, col 4	VREF
4	B14→B16	V12N
5	J19→GND top, col 19	GND
6	J22→GND top, col 22	GND
7	J25→GND top, col 25	GND
8	C19→C22	Y
9	D22→D25	Y
10	E9→F7	MZ
11	E10→G6	MN
12	E11→H5	ME
13	E12→I4	VREF
PJ	GND top, col 30→btm rail, col 30	GND · ties the two ground rails; run it beside column 30 or on the underside

Wires in

Hole	Net	From
J12	MASS_Z	sensor G · Z mass
J11	MASS_N	sensor J · N mass
J1	MASS_E	sensor L · E mass
A3	3V3	Pi 3V3 · pin 17
A5	SCL	Pi SCL · pin 5 · GPIO3
A6	SDA	Pi SDA · pin 3 · GPIO2
GND top, col 29	GND	Pi GND · pin 9
VREF rail, col 22	VREF	from ADC · VREF
A13	V12IN	adapter + · 12 V
A14	V12N	adapter − · 12 V
A16	V12N	sensor b · gnd
A17	V12	sensor c · +12
J21	GPIO_U	Pi GPIO16 · pin 36
A20	CTL_U	sensor U · + centre btn
J24	GPIO_W	Pi GPIO20 · pin 38
A23	CTL_W	sensor W · + unlock btn
J27	GPIO_X	Pi GPIO21 · pin 40
A26	CTL_X	sensor X · + lock btn
A19	Y	sensor Y · + btn com

Sensor cables

Two stranded Ethernet patch cables and a two-core power lead. At the sensor, each conductor ends in an insulated Dupont socket on its pin (letters on connector_pinface.png), with the housings retained and the bundle tied down to the floor before a loose loop. At the board box, each Ethernet cable plugs into a Cat6 keystone jack in the box’s front wall, punched down T568B, with short wires from the jack to the boards. One cable per board: SIG carries the three velocity pairs and signal ground, all to the ADC board; CTL carries the three mass positions and the control lines, all to the AUX board. Keep the three leads apart for the first half-metre from the sensor.

Pin	Function	Cable · pair · T568B pin	Lands on	Note
A	Z velocity +	SIG · orange · 1 (wh-or)	ADC A9	Each velocity pair on its own twisted pair
B	Z velocity −	SIG · orange · 2 (or)	ADC A2
C	N velocity +	SIG · green · 3 (wh-gn)	ADC A18
D	N velocity −	SIG · green · 6 (gn)	ADC A11
E	E velocity +	SIG · blue · 5 (wh-bl)	ADC A27
F	E velocity −	SIG · blue · 4 (bl)	ADC A20
N	Signal ground	SIG · brown · 8 (br)	ADC GND btm, col 24	The sensor’s only signal-ground tie
—	spare	SIG · brown · 7 (wh-br)	—	Unused; leave unpunched
G	Mass position Z	CTL · orange · 1 (wh-or)	AUX J12	All three mass positions on CTL
J	Mass position N	CTL · green · 3 (wh-gn)	AUX J11
L	Mass position E	CTL · green · 6 (gn)	AUX J1
U	Centre	CTL · blue · 5 (wh-bl)	AUX A20	OK1, and the CENTRE button to Y
Y	Logic ground	CTL · blue · 4 (bl)	AUX A19	Optocoupler emitters; the three buttons’ commons share the hole
W	Unlock	CTL · brown · 7 (wh-br)	AUX A23	OK2, and the UNLOCK button to Y
X	Lock	CTL · brown · 8 (br)	AUX A26	OK3, and the LOCK button to Y
—	spare	CTL · orange · 2 (or)	—	Unused; leave unpunched
c	Power +	power lead, red	AUX A17	Own two-core lead, not in either Ethernet cable: after D1
b	Power ground	power lead, black	AUX A16	12 V return, strip-joined to the adapter −. Goes nowhere else: the sensor ties b to its signal ground inside

Why power has its own lead: plugging SIG and CTL into each other’s jacks is then harmless. The worst a swap does is put the lock line on signal ground and lock the masses. With 12 V in an Ethernet cable, a swap would drive the sensor’s outputs from the supply. Use two cable colours and two jack colours anyway, and label both ends. If shielded cable is used, the drain goes to GND at the board end only.

Each panel button shorts its line to Y; the optocoupler beside it does the same for the Pi. Solder the button lead into the same hole as the sensor wire. The lines are active-low (idle 5 V). The 12 V adapter enters through the VIN panel jack, wired to AUX A13 (+) and A14 (−); the sensor’s power lead leaves through the VOUT jack, wired to A17 (+) and A16 (−).

Assembly and test

Stage 1ADC board

checkQuick meter check per module — The purple module ties AVDD to DVDD and pulls CLK to DGND with 10 kΩ (marked 103). Module unpowered: AVDD to DVDD ~0 Ω (Ω, 200 range), CLK to DGND ~10 kΩ (Ω, 20k range; not continuity, which can’t see 10 kΩ). It matters because AVDD gets no socket. A module that differs is a spare.
Cut the female headers — Per module: one 8-pin (digital), one 6-pin and one 1-pin (analog). Cut through a contact, not between, and sand the ends.
Jumpers 1–13 — All of them now, while the board is bare. Rail jumpers 2, 3, 5, 6, 8, 9 hop over the GND rail; keep them flat.
Bus wires B1–B6 — SCLK, MOSI and MISO from module Z to N (row H) and N to E (row G), in the free holes between the socket rows. Insulated wire on the top side, lying flat: the modules sit over them on their sockets. Not the solder side. Fit before the modules, like Cdif. Then one plain Pi lead per signal is enough.
Cdif ×3 under the modules — Lay each film cap flat with its body toward the channel, leads into E7/E8, E16/E17, E25/E26. This is the only chance to fit them.
Sockets — Solder the three 8-pin strips in row I and the 1+6 strips in row D, with a module plugged in to hold them square. Then take the modules out again. No socket at D2, D11 or D20 (the AVDD pin): those columns carry the sensor’s minus lead, and a socket there ties it to 3.3 V. If one got fitted, clip the AVDD pin off the module instead; AVDD is fed through the module’s own AVDD–DVDD link.
Dividers — Rbp flat in row B, Rb on end, Ra/Rap across the GND rail. Check each value with the meter before soldering: 4.99k and 10k 0.1% look alike.
Reference — VR1 in H27–H29 (either way round), Rfd1, Rfd2, Cref, Cd, PJ.
checkPower test, no modules, no sensor — First unpowered, Ω: A29 to VREF rail ~1.44 kΩ (2k range); 3V3 rail and VREF rail to GND not ~0 (200 range). Then Pi 3V3/5V/GND wires on, all readings on 20 V DC: 3V3 rail ~3.3 V; VREF rail = 2.50 V (the 20 V range shows 10 mV steps, the D-grade part is 1%, so anything 2.48–2.52 passes). With the sensor leads open, each AIN strip reads 2.50 V (no current in Rb). Short a sensor lead to GND and that AIN drops to 1.67 V.
Modules in, Pi wires on — Nine plain leads: CS and DRDY for each module, and SCLK / MOSI / MISO into J5 / J6 / J7 only. Register readback on each module before anything else.
checkShorted-input noise — Short each channel’s two sensor leads to GND and log ten minutes. Expect ~1.5 nm/s/√Hz equivalent at turbo 180 SPS (0.72 µV/√Hz), flat above 0.5 Hz; below that is what this test is for. Do this before the sensor is connected.

Stage 2AUX board

Jumpers first, then the resistors — RmE I5→I1, RmZ I7→I12, RmN H6→H11 (flat); Rr upright from J5, J6, J7 across the GND rail to the VREF rail; Rk1–Rk3 in row H.
Optocouplers — OK1–OK3 straddling the channel, pin-1 dot top right (in row F, on the right of each: F20, F23, F26). Rk1–Rk3 stand on end.
ADS1115 — Check the chip marking first: BOGI is an ADS1115, BRPI an ADS1015 (reject). Solder the straight 10-pin header to the board (short pins into the board), then stand it upright in D3–D12, chip side toward row A, VDD at D3. Then jumpers 10–13: E9→F7 (A0, Z), E10→G6 (A1, N), E11→H5 (A2, E), E12→I4 (A3, VREF), insulated wire across the channel.
12 V island — D1 C13→C17, band toward 17; jumper B14→B16. Nothing here touches a rail.
checkCheck before the sensor — Meter on DC V, 20 V. Adapter on A13/A14, Pi off: A17 reads ~11.6–12.3 V against A16 (12 V less the Schottky drop; unloaded adapters read high); Pi on, VREF wire in: i2cdetect -y 1 shows 0x48; with the mass inputs open, cols 7, 6, 5 (A0, A1, A2) read the same as VREF (~2.46 V; no current in Rm). Optocouplers on Ω, 2k, red probe on the collector: A20 to A19 reads open, then drops to a few hundred Ω while GPIO16 is driven high. Repeat A23 to A19 with GPIO20 and A26 to A19 with GPIO21.

Stage 3Box

checkFit test — Print enclosure/fit_test.stl (outer face down, no supports): a keystone jack must click in from behind, a DC jack and a button must go through.
Print the box — Base upright, open side up, no supports; lid flat face down. Walls 2.5 mm, honeycomb floor and lid.
Front wall — Left to right: VIN jack (12 V adapter in, AUX A13/A14), AUX keystone (CTL), ADC keystone (SIG), VOUT jack (sensor power lead, AUX A17/A16), and the three buttons above. Keystones go in from inside, latch up. Label all four.
Board stack — Four standoffs stand on the floor pads, studs down through the floor, nuts from below in the 10 mm pockets. The AUX board screws to them, the ADC board above it.
Pi on the side wall — Four standoffs through the right wall from outside, nuts inside. Pi component side out, GPIO header at the top; its wires go over the top edge into the slot in the wall.
Lid — Snaps on one way round, with its lip gap over the Pi slot. Six bumps click into the walls.

Stage 4Sensor

stopHarness: buzz it out twice — Every conductor from its Dupont socket to its board hole, against the cable table, with the patch cables plugged into their jacks. The power lead gets checked alone: red on pin c, black on pin b. A wrong c/b pair is the one mistake that can hurt the sensor.
Sensor locked, then connect — Plug in with the adapter unplugged. Adapter in: the mass positions read ±8 V on the AUX channels.
checkOptocoupler drive, before any unlock — Sensor powered and locked. Meter on DC V, 20 V, black on A19 (Y): A20, A23, A26 idle at ~5 V. Test with LOCK only, since locking an already-locked sensor changes nothing: drive GPIO21 high for 1 s; A26 must fall below ~0.8 V. If it only sags, the LED current is too low for the sensor’s pull-up: parallel a second 1 k across each of Rk1–Rk3 (4 mA). Do not pulse CENTRE or UNLOCK here; the other two optocouplers are the same part and resistor.
Unlock on its final pad — Level it with the feet and bubble, N mark to north. UNLOCK ~7 s from the button or cmgctl.py unlock: the motors run for a few minutes and the masses usually centre themselves (within ±2 V).
Centre if needed — After ~4 hours of settling, any mass beyond ±2 V: CENTRE ~7 s (cmgctl.py centre), then wait two minutes before reading again.
stopLock before moving — cmgctl.py lock, wait for quiet and all three masses at ~±8 V, then remove power. Never move it unlocked.

Raspberry Pi

Everything is 3.3 V logic; the modules have no level shifters. SCLK, MOSI and MISO each run as one plain lead from the Pi to module Z; the board’s bus wires carry them to N and E. Nineteen Pi pins in all: 9 for the three converters, 2 for I²C, 3 for lock / unlock / centre, and power.

Pi pin	Signal	Board hole	Note
1	3V3	ADC 3V3 rail, col 30	3.3 V, never 5 V, to the modules. Pi pin 17 feeds the AUX board
2	5V	ADC A29	Feeds the reference through Rfd1∥Rfd2
6	GND	ADC GND top, col 28	Pi pin 9 goes to the AUX board’s GND
23	GPIO11 SCLK	J5	One plain lead. Bus wires B1/B2 carry it on to N and E
19	GPIO10 MOSI	J6	One plain lead; bus wires B3/B4
21	GPIO9 MISO	J7	One plain lead; bus wires B5/B6. DOUT is high-impedance while CS is high, so sharing is safe
18	GPIO24	J4	CS Z (as on the geophone station). None of the three is a hardware CE pin: open the bus with `no_cs` and drive them by hand
22	GPIO25	J13	CS N
29	GPIO5	J22	CS E
13	GPIO27	J8	DRDY Z
15	GPIO22	J17	DRDY N
31	GPIO6	J26	DRDY E
3	GPIO2 SDA	AUX A6	I²C1; the ADS1115 board has its own 10 k pull-ups
5	GPIO3 SCL	AUX A5
17	3V3	AUX A3	ADS1115 VDD
9	GND	AUX GND top, col 29
36	GPIO16	AUX J21	CENTRE: high for 7 s. Low, the power-on default, leaves the line alone
38	GPIO20	AUX J24	UNLOCK
40	GPIO21	AUX J27	LOCK

ADS1220 registers, all three modules

Reg	Write	Fields	Why
0x00	0x01	MUX 0000 · GAIN 000 · PGA_BYPASS 1	AIN0 against AIN1, gain 1, PGA out
0x01	0x50	DR 010 · MODE 10 · CM 0	Turbo, single-shot: the Pi starts all three together at 150 SPS. Normal mode at a similar rate measured ~7× noisier
0x02	0x00	VREF 00	Internal 2.048 V reference
0x03	0x00	—	DRDY on its own pin

Write all four with 0x43 0x01 0x50 0x00 0x00 and read back with 0x23. pi/cmgcapture.py sends START to all three on each tick, reads them once all three DRDY lines are low, and resamples to 100 SPS; no SPI traffic overlaps a conversion. On a Pi 5, set pcie_aspm=off (see pi/README.md).

Notes

No series resistance in the sensor’s 12 V

The 3T runs off an internal switching supply, which draws more current as its voltage sags. A 10 Ω sense resistor in series runs away (180 mA and climbing). Only the diode sits in the line, and the adapter’s 1 A limit is the protection.

The 12 V return goes to pin b and nowhere else

The adapter− (A14) connects only to sensor pin b (A16). The sensor ties b to its signal ground internally, and signal ground N lands once, on the ADC board. So the 400–600 mA motor pulses never flow through either board’s ground.

Optocouplers keep the Pi off the sensor’s control lines

The Pi only lights an LED; the LTV-817’s transistor does the pulling, from the line to Y. The GPIOs default low at power-on, so a boot or a crash cannot lock or unlock the masses.

Why the AVDD socket is left out

Three modules take 24 of 30 columns, and each needs two strips of its own for the sensor leads. Leaving AVDD unsocketed frees its strip for the minus lead, and the minus-leg resistor lies flat over the four unused module strips. AVDD is still powered through the module’s own AVDD–DVDD tie, so meter that before building.

No Ccm capacitors

No 10 nF from each input to ground: the layout has no clean spot for six, and the 3T’s outputs are low-impedance, band-limited, and arrive over shielded cable. Cdif across each pair does the filtering the switched-capacitor input needs, since the PGA is bypassed.

PGA bypassed, gain 1

Both legs swing, so the common mode moves with the signal, and the PGA’s input limits would clip early. With the PGA out, only the pin limits apply: the inputs stay inside 0–3.3 V until ~6.7 mm/s, beyond the ±4.1 mm/s full scale.

Matched pairs are what reject the reference

VREF noise reaches both legs of a channel equally and cancels in the differential reading, to the extent the pairs match. That is what the 0.1% parts buy; the 1% mass-position dividers don’t need it.

Boards in a closed box, Pi outside it

Below ~0.05 Hz, the limit is the boards’ thermal drift, not the converter. The printed box keeps air movement off them, and the Pi, the main heat source, sits outside on the wall.

Pi 5: PCIe ASPM off

With ASPM on, the PCIe link to the RP1 (the chip behind the GPIO and SPI pins) drops into L1 between reads and puts an ~80 ms disturbance on all three channels every 2.77 s. Add pcie_aspm=off to /boot/firmware/cmdline.txt.